The present invention relates to integrated circuit devices and more particularly integrated circuit devices including isolated active regions and methods for manufacturing the same.
Various integrated circuit devices, including semiconductor memory devices, include a plurality of active regions in which one or more devices, such as transistors, are formed. In general, isolation regions are provided to define these active regions and to electrically isolate the active regions from each other. Various approaches to providing such isolation regions are known, including local oxidation of silicon (LOCOS) and a trench method. In particular, it is known to use shallow trench isolation (STI), which may be used to provide a larger active region than other trench methods.
Nonetheless, as the integration density of integrated circuit devices increases, even when STI is used to provide isolation regions, the area of active regions occupied by individual devices can decrease geometrically. When the area of active regions occupied by individual devices decreases, and the individual devices are short-channel transistors, a reverse narrow width effect may result as the threshold voltage for the active regions may also rapidly decrease. More particularly, when the area of an active region becomes narrower, a corner transistor (i.e., a transistor formed at an edge of the active region) may use a larger percentage of the active region than a flat transistor (i.e., a transistor formed at the center of the active region). Because the threshold voltage Vt1 of the corner transistor (Corner Tr.), as shown in FIG. 1, is typically lower than the threshold voltage Vt2 of the flat transistor (Flat Tr.), the characteristic threshold voltage of transistors formed on the active region generally becomes lower. It is this lowered characteristic threshold voltage result that is referred to herein as the reverse narrow width effect.
One proposed method to prevent or reduce such a reverse narrow width effect is channel ion implantation, where ions are implanted into the channel region of a transistor. However, the use of channel ion implantation may deteriorate the static refresh characteristics of an integrated circuit device, such as a dynamic random access memory (DRAM).
An alternative approach is to decrease the area of the isolation region. However, using such an approach, the isolation region may fail to provide the desired dielectric characteristics between active regions. One known method for controlling the dielectric characteristics of an isolation layer, while relatively increasing the area of an active region, will now be described with reference to FIGS. 2A and 2B.
As shown in the cross-sectional schematic diagram of FIG. 2A, a pad oxide layer 12 and a silicon nitride layer 14 are sequentially deposited on an integrated circuit (semiconductor) substrate 10. Predetermined portions of the silicon nitride layer 14 and the pad oxide layer 12 are patterned to expose an area on which an isolation layer will be formed. Next, a predetermined material layer is deposited over the integrated circuit substrate 10. This material layer is patterned so as to be left only at the sidewalls of the silicon nitride layer 14 and the pad oxide layer 12 to form spacers 16. The material layer used in forming the spacers 16 may be, for example, a silicon nitride layer or a polyimide layer that has superior etching selectivity with respect to a silicon or silicon oxide layer. The integrated circuit substrate 10 is then etched to a predetermined depth using the pad oxide layer 12, the silicon nitride layer. 14, and the spacers 16 as an etching mask, thereby forming a trench 18.
As shown in FIG. 2B, an insulating layer 19 is deposited on the integrated circuit substrate so that the trench 18 is filled with the insulating layer 19 to a desired depth. The insulating layer 19, the silicon nitride layer 14, the pad oxide layer 12 and the spacers 16 are then chemically and/or mechanically polished, until the surface of the semiconductor substrate 10 is exposed, to form an isolation layer.
The isolation region formed using such a conventional manufacturing method may have various problems. For example, because the spacers 16 are formed of a layer having superior etching selectivity with respect to a silicon or silicon oxide layer, as described above, there typically will also be a difference in polishing selectivity between the spacers 16, the pad oxide layer 12, and the insulating layer 19. This may create problems when polishing the insulating layer 19 filling the trench 18, the silicon nitride layer 14, the pad oxide layer 12, and the spacers 16 as, in order to expose the surface of the integrated circuit substrate 10, the amount of polishing typically will have to be selected to remove the spacers 16, which have a relatively low polishing selectivity.
Due to the amount of polishing required to remove the spacers 16, the integrated circuit substrate 10 under the spacers 16 may be damaged. Thus, portions “A” of the integrated circuit substrate adjoining the edge portion of the trench 18 may be removed. As a result, the insulating layer 19 may be buried in these unintentionally removed portions of the integrated circuit substrate 10. Thus, the edge portion of the trench 18 may become part of an active region and the area of the active region may be substantially decreased. In addition, because the thickness of the insulating layer at the edge portion of the trench 18 is relatively thin, an electric field may be concentrated on the thin portion of the insulating layer. As a result, the electrical characteristics of the insulating layer at the edge portion of the trench 18 may deteriorate.